# Modular RISC Machine: Design Process

#### Written 2009-07-16

#### Tags:Hardware Reduced instruction set computing Components

So, I'm going to build this little modular RISC machine.

Core isn't the right word for a division in this processor. I think `Channel`, is a bit more accurate. Although the design should scale for an arbitrary number of channels, and for channels with an arbitrary bit width, I plan to make a dual-channel, 4bit channel demonstration( an 8 bit computer). With any luck, I should be able to extend the design to a 16 bit computer, which is the limit of the largest SRAM I've been able to find for a low price. So the sections I need to design/purchase:

Core isn't the right word for a division in this processor. I think `Channel`, is a bit more accurate. Although the design should scale for an arbitrary number of channels, and for channels with an arbitrary bit width, I plan to make a dual-channel, 4bit channel demonstration( an 8 bit computer). With any luck, I should be able to extend the design to a 16 bit computer, which is the limit of the largest SRAM I've been able to find for a low price. So the sections I need to design/purchase:

- Modular Program Counter, parallel load, with Overflow output.
- Modular ALU with carry-in and carry-out
- Registers
- Control Unit
- 2->1 Multiplexers
- TriState Buffers

- 3 Registers
- 1 ALU
- 1 Program Counter
- 1 Address Latch