Volume of Spheres to Cubes Over Varying Dimensions.

Written 2014-07-06

Tags:Math n-Ball Hypercube Dimension Hypersphere 

As James Jolly said(approximately) to me, as the number of dimensions goes up, a normally-distributed dataset's points become closer together. To approximate it, draw a circle in a square, followed by a sphere in a cube, followed by a hypersphere in a hypercube. This relationship wasn't intuitively apparent to me, so I plotted it out.
polydimrat output

Some Intuition

To think recursively, each next-higher dimension contains an infinitely thin slice of the current dimension. For example, in three dimensions, a the area of a circle cut through a unit sphere by a plane of z=0 is the same area as a 2-dimesional unit circle. This is true all the way down - a 1-dimensional circle fills the 1-dimensional space from the leftmost to the righmost points on the 2-dimensional circle.

Intuition at the Equator

plot_3d

Intuition at z=-0.75

plot_3d_threeQuarters

But, we may notice that the ratio of circle-to-square in our slice is highest only in the middle(z=0). By varying from the center of our dimension-splitting subregion that ratio in the slice is always smaller. This is also true for the ratio of sphere-to-square in any two neighboring dimension sets(n->n+1). By approximating an integral, if the highest ratio in a dimensional space is the ratio in the lower dimensional space, and our integral averages over all the current space, then the ratio in the current space must go down, as being an average of ranges between 0 and the ratio of the previous space.

STREAM:UltraSPARC IIIi vs UltraSPARC T1

Written 2014-06-21

Tags:SPARC benchmark STREAM computing 

Today, I ran STREAM on my old router(Sun V210, 2x UltraSPARC IIIi) and my new one(Sun T2000, 1xNiagara T1).

Benchmark Overview

STREAM is a simple memory bandwidth benchmark. It conducts a series of operations on large vectors of variables and reports back on how long the operations took, as well as a double-check to ensure the results are correct. The tests are:
  • Copy: Y[] = X[]
  • Scale: Y[] = X[]*n
  • Add: Y[] = X[]+Z[]
  • Triad: Y[] = X[]*n+Z[]
The Copy test almost always gets optimized to a memcpy, which serves as a good reference for systems with weak FPU performance, or with no FPU at all. All other tests tend to make heavy use of any available FPU.

System Overview

V210

The V210 uses two UltraSPARC IIIi CPUs attached to DDR memory. Each IIIi supports a single core with FPU.

T2000

The T2000 uses a single UltraSPARC T1 CPU attached to DDR2 memory. The T1 supports four cores each with eight threads, but with only a single FPU. Effectively up to 32 independently schedulable threads. The T1 is also known for slow single-threaded performance, a design corrected in the T4 and newer CPUs.

STREAM Results in Megabytes/Second

Box: V210x1V210x2T2000x1T2000x32
Copy: 496.7 577.5 429.6 3492.9
Scale:498.3 568.0 261.2 1558.7
Add: 494.1 597.1 282.8 2133.4
Triad:419.3 579.5 220.9 1176.8

Single-Threaded Results

V210

What can I say? This router is getting old.

T2000

The T1's single-threaded results are bad - even worse than the IIIi(a 4 year older design). This could prove to be a problem, as in addition to routing, I'll need it to run a few mostly single-threaded game servers as well. More measurements required.

Relative Multi-Threading Improvement over Single-Threading

Box: V210x2T2000x32
Copy: 1.16 8.13
Scale:1.14 5.97
Add: 1.21 7.54
Triad:1.38 5.33

Multi-Threaded Results

V210

A little bit faster, but not a whole lot. This usually means that one thread is capable of nearly saturating the memory bus/controller, which is good - it implies that the penalty for the extra multithreading hardware is relatively cheap, although it could also mean your memory controller or cache just isn't very good.

T2000

This is where the T1 shines, with between 5.3x and 8.1x more bandwidth usage spread over 32 threads. What's interesting here, is that the overall improvement was greater than 4x(number of cores). This means that a hardware thread isn't capable of saturating the bandwidth for the local core, and so 8 or more threads will be required for saturating the chip's bandwidth and that may only occur if the kernel schedules them 2-to-a-core.

Detecting Exceptions on OpenBSD and MIPS

Written 2014-06-18

Tags:Interrupt MIPS Exception OpenBSD 

The MIPS processor exception handling sequence uses two reserved general-purpose registers, k0 and k1. When the exception occurs, the core jumps to the exception handler address, then using only k0 and k1, the handler must save enough state to handle the exception. To prevent information leakage from kernel-space to user-space, OpenBSD clears k0 and k1 to zero near the end of the exception handler. By populating k0 or k1 with a non-zero value, we simply need to poll one to detect when an exception occurs.

IT-24 Image Scraper Now Supports More Analyzers

Written 2014-03-16

Tags:AA-170 Ham Radio Antenna IT-24 WiFi HSMM RigExpert 

The IT-24 Image Capture tool has been updated to support AA-170 analyzers as well. The AA-170 analyzer uses a 128x64 1-bit display, a simpler image transfer protocol, and a slower baud-rate. The new baud-rate must be specified on the command-line.

Additionally, this software should work on several other RigExpert analyzers like the AA-30 and AA-54, and may work with AA-230 and AA-520 as well. If you have one of the above analyzers, I'd love to hear if it works.

Inside the IT-24 Antenna Analyzer

Written 2014-03-14

Tags:Ham Radio Antenna IT-24 WiFi HSMM RigExpert 

Introduction

RigExpert makes an affordable 2.4GHz analyzer. In an earlier post I documented the image transfer protocol. Today I take it apart.

First Remove the Six Screws From the Rear of the Unit

Pop Off the Rear Case

Remove Four More Screws to Free PCB

Flip PCB into Rear Case to See Front of PCB

Overview

Although RigExpert hasn't yet published repair diagrams or schematics for the IT-24, the design seems fairly simple and easy to repair. The main sections are RF(back of PCB near top), display(front of PCB near top), power(front of PCB near bottom), and digital/micro(back of PCB near bottom). There's a JTAG header to the ATMEGA128A, and except for the micro and FTDI converter, the other components are large enough to be manipulated with an iron. It would've been nice if the battery pack were attached with a connector instead of soldering. Coax-connectors are a standard part, which is great, since SMA and RP-SMA connectors are only rated for around 500 insertions. At one insertion per workday, they'll need replacement around every two years.

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